Application of Capacitance Error Averaging Technology in Pipeline ADC
Time：2021.11.11
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1 Introduction
With the wide application of digital signal processing technology in wireless communication and other fields, people have higher and higher requirements for the speed and accuracy of analog-to-digital converters (ADC). However, due to considerations such as power consumption and cost, the reduction of device size and power supply voltage makes the design of high-speed and high-precision ADCs more and more challenging. Among the various types of ADCs, the pipeline structure (pipeline) ADC well coordinates the contradiction between area and speed. It has relatively low power consumption and chip size, and can achieve a higher conversion rate. However, when implementing high-resolution pipelined ADCs, errors caused by device mismatch and other factors (such as threshold shift caused by comparator voltage offset, capacitance mismatch, etc.), if not eliminated, will have a serious impact on ADC performance. . Therefore, in order to reduce the error and make the ADC achieve higher effective accuracy to meet people's demand for high-precision modern data acquisition systems, many on-chip calibration techniques have been developed. Although these calibration techniques have their own characteristics, they can generally Divided into the following two categories: on-chip analog calibration; on-chip digital calibration. In addition, there is an important type of calibration technology-Capacitance Error Averaging (CEA) technology. The CEA technology has always been considered as a method of analog calibration, but in 2006, the digital capacitance averaging technology was proposed, so that its existing implementation methods include both analog calibration and digital calibration. This article briefly introduces the principles and characteristics of various methods in the capacitance error averaging technology, and then looks forward to its development trend.
2 Structure of pipeline ADC
Although the actual pipeline ADC should be a fully differential structure, due to the symmetry of the circuit, this article only analyzes the principle of single-ended (except for active error averaging technology). As shown in Figure 1, the entire circuit consists of a sample-and-hold circuit and N-bit identical sub-level circuits. Each of its children works on the same principle:
(1) Sampling phase: The upper-level output Vi-1 is sampled by capacitors C1 and C2, and Vi-1 passes through two comparators to generate the output code qi (qi=-1, 0, or 1) of this stage. And it can be derived from this that the digital output result CR of the entire pipeline is:
(2) Amplification phase: The capacitor C1 is connected with the amplifier output to form a feedback loop, and the capacitor C2 is connected with the voltage qiVref determined by the output code of this stage. At this time, the output generated by the amplifier is:
Under ideal conditions, the capacitance can be well matched, that is, the capacitance C1=C2. At this time, the ideal transmission characteristic curve is shown in Figure 2. At the same time, the residual output Vi of this stage is:
It can be seen from the comparison of formula (2) and formula (3) that the capacitance mismatch will cause errors in the residual output, which will affect the accuracy of the ADC.
3 Introduction to Capacitance Error Averaging Technology
The capacitance error averaging technique is an important calibration method that is not sensitive to temperature and aging. The basic idea is to use capacitor exchange to obtain two outputs with complementary errors, and then average to change the original error from first-order to high-order, thereby obtaining a more accurate output.
3.1 Active capacitance error averaging technology
Active Capacitor Error-aver-aging technique (ACEA), its circuit structure is basically the same as the standard pipeline ADC, the difference is that it adds an error averaging amplifier after the redundant amplifier. At the same time, the clock changes from 2 phases to 3 phases, which are sampling phase, amplification phase and average phase. The working process is shown in Figure 3. Since there is a mismatch between the capacitors in the actual circuit, it is assumed that the capacitors connected to the input of the redundant amplifier and the average amplifier are capacitors C and C(1+α) and C1 and C1(1+β), α And β are the mismatch coefficients of the capacitors.
In the sampling phase, the input voltage Vi-1 is sampled by the capacitors C and C(1+α); then in the amplification phase, the capacitor C(1+α) is connected to the voltage qiVref, and the redundant output generated by the redundant amplifier is then There is a difference in the actual ideal value. From equation (2), it can be seen that the output Uo1 is actually the inter-stage output without calibration. At the same time, Vo1 is cross-sampled by the subsequent capacitors C1 and C1(1+β). The expression is:
Finally, it enters the average phase. Because the connection relationship between the capacitors C and C(1+α) is interchanged, and the capacitor 2C1 is connected with the average amplifier output to form a feedback loop, the redundant output generated by the redundant amplifier and the final average amplifier output are :
It can be seen from the above analysis that the final output expression (6) compared with the output without calibration, the error is changed from first-order to second-order. Assuming that the mismatch coefficient β is 3%, it can be seen that the error after calibration is reduced to 3% before the calibration, so as to achieve the purpose of calibration.
3.2 Passive capacitance error averaging technology
Although the correct output can be obtained through ACEA technology, this is at the cost of multiplying the complexity of the circuit. As a result, Chiu proposed a passive capacitance error averaging technology, referred to as PCEA technology. He used double sampling to replace the error averaging circuit in ACEA technology, which greatly reduced the circuit scale.
Figure 4 is a schematic diagram of this PCEA technology. The basic structure of the circuit is exactly the same as without calibration, but each conversion cycle is composed of 2 sampling phases and 2 transition phases. The input Vin1 and Vin2 in the figure are the complementary output of the second-order error of the transition phase of the previous stage circuit. If it is the first stage circuit, the input Vin1=Vin2 is the output of the sample-and-hold circuit.
For the convenience of explanation, suppose Vin1=Vin2=Vi-1. The analysis shows that the two output voltage values of Vo1 and Vo2 of the i-th stage in the transfer phase 1 and the transfer phase 2 are the same as the Vo1 and Vo2 in the analysis of the active capacitance error average principle, which are respectively equations (4) and (5). Obviously, the errors of Vo1 and Vo2 are complementary. Because Vo1 and Vo2 are sampled by the capacitors C1 and C1(1+β) of the next stage at the same time, the equivalent output residual voltage on C1 and C1(1+β) after charge sharing is:
Obviously, it can be seen that the error voltage changes from the first order in formula (4) and formula (5) to the second order in formula (7), so as to achieve the purpose of averaging the capacitance error. Compared with active technology, passive technology reduces the scale of the circuit by nearly half, so it can achieve the purpose of reducing power consumption, area and noise. However, because a conversion cycle requires 4 clock phases, the analog/digital conversion speed is twice as slow as when it is not calibrated, so it is suitable for occasions where the speed is not high and the power consumption and resolution requirements are high. It is worth mentioning that due to the low performance of PCEA technology in terms of speed, literature [5, 6] proposes an improved PCEA technology, which improves the performance of speed and other aspects to a certain extent.
3.3 Digital capacitance error averaging technology
Because ACEA technology and PCEA technology both need to increase the extra clock phase while working, reduce the conversion speed, O. Bernal et al. proposed a digital capacitance error averaging (Digital Capacitor Error-averaging technology, DCEA) technology. This technique adopts the idea of the above-mentioned analog capacitance error averaging technique and realizes it in the digital domain. He uses the principle of capacitance error averaging to obtain the proofreading coefficients. In the proofreading process, these constants are called according to the output of each level. Because DCEA technology does not need to add extra clock phase, its speed can reach 2 times of PCEA technology (as shown in Table 1). The following is the working principle of DCEA technology.
According to formula (2), let C1=C(1+α) and C2=C(1-αi). For the convenience of algorithm explanation, the capacitance mismatch coefficient here is defined as 2αi. It can be derived from this:
The calibration process of the DCEA technology is similar to the look-up proofreading method in the literature, starting from the lowest bit and ending with the highest bit. He successfully transferred the contradictions in the analog domain of CEA technology to the digital domain. And through effective digital operation to solve it, so that the performance of the circuit is improved.
4 Summary and outlook
This article mainly introduces the application of 3 different capacitance error averaging techniques in pipeline ADC. Among them, ACEA is a typical analog calibration technology, which needs to add additional analog circuits and additional clocks to achieve; although PCEA does not need to add additional analog circuits, it requires more clocks to process than ACEA, so it is essentially The category of analog domain; and DCEA technology belongs to the digital calibration method. From the development of ACEA technology to DCEA technology, the calibration method has also transitioned from analog calibration to digital calibration, and the improvement of circuit performance is obvious. As people continue to improve the accuracy and speed of the pipeline ADC, the research on its error calibration technology is also changing day by day. Because digital calibration can relatively bring lower power consumption, smaller area and greater design flexibility, it can provide a broader space for the development of calibration technology. In short, with the application of new calibration techniques and the development of integrated circuit technology, pipeline ADCs will surely make continuous progress in the direction of low power consumption, high speed and high precision.
