DC/DC Converters Research Guide - Serial 3
Time：2023.02.22
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DC/DC Converters Research Guide - Serial 3
5. Selection of switching frequency
DC/DC converter IC has an inherent switching frequency, and the frequency difference will affect various characteristics. In general, differences in switching frequency affect the various characteristics shown in Table 2.
FIG. 7 to FIG. 8 take XC9237A18C(1.2MHz) and XC9237A18D(3MHz) as examples to show the relationship between switching frequency and efficiency. Efficiency clearly shows the results shown in Table 2. The most efficient current value is different because different switching frequencies are suitable for different induction coefficient values. For coils with the same structure, the greater the induction coefficient, the greater the DC resistance, and the greater the loss under heavy load. Therefore, the more low-frequency current value with the highest efficiency, the more it will move to the light load side. On the contrary, due to the increase of charge and discharge times of FET and the increase of static consumption current of IC itself, the efficiency of 3MHz product is significantly worse than that of 1.2MHz product at light load. Taking these effects into account, it can be seen that the maximum efficiency of 1.2MHz products is large (= the maximum peak value of the efficiency diagram), while the output current value of the maximum efficiency is small (= the peak value of the efficiency diagram is left). In addition, the PFM operating, light load frequency is further reduced, the efficiency is significantly improved.
6. Choice of FET
For the absolute maximum rating of voltage and current, choose to reduce the switching peak noise and pulse noise failure rate for the purpose of the rating is about 1.5 times ~ 2 times of the voltage in use, R DS and C ISS caused by the minimum loss of products, can form a DC/DC converter circuit with good efficiency. The smaller the R, DS, and C, ISS, the smaller the loss, but since R, DS, and C, ISS are inversely proportional, the greater the loss, the better. The loss caused by C ISS is the power discarded during charge and discharge between grid source electrodes of the FET, which can be expressed as C ISS V GS2 f/2. The greater the driving voltage and switching frequency, the greater the loss, because heavy load and light load loss value is basically the same, so it will make the efficiency of light load significantly worse.
The loss caused by RDS is emitted as the heat generated by the resistance component between the drain-source electrode of the FET. Its value is expressed by I D2 RDS, and the greater the load, the greater the value. Therefore, it can be said that reducing the loss caused by C ISS under light load has a better effect on improving efficiency, while reducing the loss caused by R DS under heavy load has a better effect. The above are summarized in Table 3 below.
Input current can be calculated by output (load) current × output voltage ÷ input voltage ÷ efficiency. When the efficiency is unknown, 70% can be used for pressure boost and about 80% can be used for pressure drop.
Figure 10 is an efficiency diagram of the XC9220C093 test with only the FETs replaced in the peripheral components shown in Figure 11. The specifications of the FETs used are shown in Table 4. As can be seen from FIG. 11, the use of Fets with small R DS shows a tendency to drive larger current and improve efficiency under heavy load. But also
It is known that further greatly reducing the efficiency of light load, unnecessary use of current drive capacity of large FET is inappropriate.
The above content is from Tris Semiconductor Co., LTD. In the series...
